For example, in forming device regions in a semiconductor substrate, a large number of pn junctions are used. An SOI (silicon on insulator) with a silicon thin film formed on a substrate surface through an insulating film has been widely employed for several semiconductor devices such as DRAM. Further, a glass substrate with a semiconductor thin film formed on a substrate surface is widely noticed by attempting miniaturization and high speed of a liquid crystal panel through integration of a driving circuit of liquid crystal including a thin film transistor (TFT) in the semiconductor thin film.
As described above, in forming various semiconductor devices, pn junctions are employed. In order to form these pn junctions, traditionally, a method has been adopted in which after p-type impurities such as boron are introduced in an n-type Si substrate thorough ion implantation, they are electrically activated by a halogen lamp.
For example, as a method for introducing boron that is the p-type impurities, in addition to the ion implantation, plasma doping is expected as a next-generation method capable of effectively introducing particles with very low energy.
As a method for electronically activating the ions such as the boron ions introduced, a method for applying xenon flash lamp light, entire-solid laser light or excimer laser light in addition to halogen lamp light has been researched and developed.
All the xenon flash lamp light, solid laser light and excimer laser light have an intensity peak at a shorter wavelength than the halogen lamplight. For example, the conventional halogen lamp light has the intensity peak at 1000-1100 nm, whereas the xenon lamp light has the intensity peak at the wavelength of 400-500 nm and the excimer laser light has the intensity peak at the wavelength of 400 nm or less. Since they have the peak at a shorter wavelength, they can be effectively absorbed in silicon (Si) (see Non-patent References 1 and 2). Thus, by absorbing light energy at a shallow portion in a substrate surface, a shallow activated layer can be formed.
Further, a method has been also proposed for forming a shallow activated layer using a difference in a light absorption coefficient between silicon crystal and amorphous silicon. Specifically, in a wavelength range of 375 nm or longer, the amorphous silicon has a larger light absorption efficient than the silicon crystal. Thus, an amorphous layer is previously formed on a Si substrate surface before irradiated with light, and thereafter light is applied to cause the amorphous layer to absorb more light energy, thereby making a shallow activated layer. The amorphous layer is formed by ion-implanting e.g. germanium (see Non-patent References 1, 2, 3, 4 and 5).
By these research researches, a result has been reported in which the light with a shorter wavelength ranging from 375 nm (inclusive) to 800 nm (inclusive) is applied to cause the substrate to effectively absorb the light energy, thereby making a shallow junction (see Non-patent References 1 and 2). In these reports, generally, prior to introduction of impurities, the substrate surface is previously changed to be amorphous and thereafter the impurities are introduced. In this case, for impurity introduction, ion-implantation of BF2+ or B+ is adopted and for previous amorphous-changing, ion-implantation of germanium or silicon is adopted. Namely, ion implantation must be twice carried out. This led to a problem that the process is complicated. Further, in order to make the shallow junction, in the case of ion-implantation of BF2+ or B+, an accelerating voltage must be lowered to several hundreds V so that the beam current value is lowered. This led to a problem of low throughput. Furthermore, since there are many combinations of twice-ion-implantation conditions and the methods for introduction and electronic activation of boron are often individually researched and developed, under present circumstances, the state of the substrate surface suitable to the wavelength of an electromagnetic wave to be applied is not still known.
Non-patent Reference 1: Ext. Abstr. of IWJT, pp 23-26, Tokyo, 2002.
Non-patent Reference 2: Symposium on VLSI Technology Digest of Technical Papers, pp 53-54, Kyoto, 2003.
Non-patent Reference 3: Ext. Abstr. of IWJT, pp 31-34, Tokyo, 2002.
Non-patent Reference 4: Ext. Abstr. of IWJT, pp 27-28, Tokyo, 2002.
Non-patent Reference 5: 2000 International Conference on Ion Implantation Technology Proceedings, 2000, pp. 175-177.